Filling vacant areas of an integrated circuit design

ABSTRACT

Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application is a continuation of U.S. patent applicationSer. No. 15/709,376, filed Sep. 19, 2017, issued as U.S. Pat. No.10,691,858 on Jun. 23, 2020, which is a divisional of U.S. patentapplication Ser. No. 13/909,872, filed Jun. 4, 2013, issued as U.S. Pat.No. 9,767,242 on Sep. 19, 2017, which is a divisional of U.S. patentapplication Ser. No. 12/727,227, filed Mar. 18, 2010, issued as U.S.Pat. No. 8,458,636 on Jun. 4, 2013, which claims the benefit of U.S.patent application 61/161,308, filed Mar. 18, 2009. These patents areincorporated by reference along with all other references cited in thisapplication.

BACKGROUND OF THE INVENTION

The present invention relates to the field of electronic designautomation for integrated circuit, and in particular, to filling vacantareas of a routed design with metal attached to power or ground.

Integrated circuits are important building blocks of the information ageand are critical to the information age, affecting every industryincluding financial, banking, legal, military, high technology,transportation, telephony, oil, medical, drug, food, agriculture,education, and many others. Integrated circuits such as DSPs,amplifiers, DRAMs, SRAMs, EPROMs, EEPROMs, Flash memories,microprocessors, ASICs, and programmable logic are used in manyapplications such as computers, networking, telecommunications, andconsumer electronics.

Consumers continue to demand greater performance in their electronicproducts. For example, higher speed computers will provide higher speedgraphics for multimedia applications or development. Higher speedinternet web servers will lead to greater on-line commerce includingon-line stock trading, book sales, auctions, and grocery shopping, justto name a few examples. Higher performance integrated circuits willimprove the performance of the products in which they are incorporated.

Large modern day integrated circuits have millions of devices includinggates and transistors and are very complex. As process technologyimproves, more and more devices may be fabricated on a single integratedcircuit, so integrated circuits will continue to become even morecomplex with time. To meet the challenges of building more complex andhigher performance integrated circuits, software tools are used. Thesetools are in an area commonly referred to as computer aided design(CAD), computer aided engineering (CAE), or electronic design automation(EDA). There is a constant need to improve these electronic automatictools in order to address the desire to for higher integration andbetter performance in integrated circuits.

An integrated circuit may be specified using a netlist and a layout. Thenetlist provides information about devices or components of theintegrated circuit and their connectivity. The integrated circuit layoutor integrated circuit mask layout is the representation of an integratedcircuit in terms of planar geometric shapes, patterns, and features thatcorrespond to shapes used in a mask to fabricate the circuit. A designengineer or mask designer may create the layout the integrated circuit.Some features in the layout or certain masks may be automaticallygenerated, such as automatically routed.

In a typical layout, there are a very large number of shapes, patterns,and features. It may be desirable (or required) to fill vacant areas ofa routed design with metal (or any other material) attached to power andground (or other desirable connection). This process is often carriedout by layout engineers manually drawing shapes in unused areas, whiletrying to conform to the layout design (or DRC) rules. As can beappreciated, this manual process is very time consuming

Therefore, there is a need for improved technique for filling vacantareas of integrated circuit design, especially where these vacant areasare filled with metal or another conductor connected to a supply linesuch as power or ground.

BRIEF SUMMARY OF THE INVENTION

Vacant areas of a layer of an integrated circuit design are filled withshapes connected to the appropriate nets. The layer may be a metal orother conductor layer. The generated shapes can be connected to power orground.

In an implementation, a method includes: for a first layer of anintegrated circuit design, using a computer, creating a first rectangleto cover a region of the integrated circuit design; determine where thefirst rectangle overlaps a previously drawn second rectangle on thefirst layer; oversize the second rectangle to obtain a third rectangle;subtract the third rectangle from the first rectangle to form a fourthrectangle, fifth rectangle, and sixth rectangle, where the fourth,fifth, and sixth rectangles each have a smaller in area than the firstrectangle and the fourth, fifth, and sixth rectangles overlap; if thesixth rectangle has a smaller width than a first minimum width, discardthe third rectangle while keeping the fourth and fifth rectangles;starting with an edge of the forth rectangle, growing an island thatextends from the edge to a limit line at a second minimum width;discarding portions of the fourth and fifth rectangles beyond the limitline to obtain a first shape including rectangles; and finding a secondshape on a second layer, different form the first layer, that overlapsthe first shape.

The method includes creating a via shape on a third layer, differentfrom the first and second layers, that overlaps both the first andsecond shapes. The method includes: finding a third shape on the secondlayer overlaps the first shape, where the second shape is connected to afirst power net and the third shape is connected to a second power net,different from the first power net; permitting specifying of a firsttarget percentage for the first power net and a second target percentagefor the second power net; determining a third percentage of shapes addedthe free space of the first layer that are connected to the first powernet and a fourth percentage of shapes added the free space of the firstlayer that are connected to the second power net; when the thirdpercentage is less than the first target percentage by more than thefourth percentage is less than the second target percentage, adding avia shape to a third layer that overlaps the first and second shapes;and when the fourth percentage is less than the second target percentageby more than the third percentage is less than the first targetpercentage, adding a via shape to the third layer that overlaps thefirst and third shapes.

The method includes discarding a rectangle of the first shape that has awidth less than a third minimum width. The method includes removing aportion of a rectangle of the first shape that has a greater than afirst maximum distance beyond a via shape connecting the first andsecond shapes. The second shape can be automatically generated by thecomputer on the second layer. The method includes forming a connectingof the second shape to the first shape using a via shape; determiningwhether the second shape is has a further connecting to a third shape ona third layer, different from the first and second shapes; and if thesecond shape does not have a further connecting to a third shape,discarding the second shape and the via shape.

The method includes: forming a connecting of the second shape to thefirst shape using a via shape; determining whether the second shape ishas a further connecting to a third shape on the second third layer; andif the second shape does not have a further connecting to a third shape,discarding the second shape and the via shape. The method includes:finding a third shape on a first layer that is identified as a powernet; and adding a seventh rectangle to connect the first and thirdshapes directly together.

In another implementation, a method includes: using a computer,automatically creating a first shape including rectangles that isrepresentative of free space on a first layer of an integrated circuitdesign; automatically creating a second shape including rectangles thatis representative of free space on a second layer of the integratedcircuit design, where the second layer is different from the firstlayer; and automatically creating a first via shape in a third layer,different from the first and second layers, that overlaps both the firstand second shapes.

The method includes: determining whether the first shape is furtherconnected to a third shape on a fourth layer, different from the firstand second layers; and if the first shape does not have a furtherconnecting to a third shape, discarding the first shape and the firstvia shape. The method includes: determining whether the first shape isfurther connected to a third shape on the second layer; and if the firstshape does not have a further connecting to a third shape, discardingthe first shape and the via shape.

A distance from a leftmost edge the first shape to a rightmost edge ofthe first shape may not exceed a maximum width specified for theautomatic creation. The method includes: when the first and secondshapes do not overlap, finding a third shape on the second layer thatwas not automatically generated; automatically creating a second viashape in the third layer that overlaps both the first and third shapes.The method includes upon request by a user, showing only theautomatically generated shapes of the first layer on a display of thecomputer.

In another implementation, a method includes: using a computer,automatically creating a first shape including rectangles that isrepresentative of free space on a first layer of an integrated circuitdesign; finding a second shape and a third shape a second layer of theintegrated circuit design that both overlap the first shape, where thesecond layer is different from the first layer; determining the secondshape is connected to first power net and the third shape is connectedto a second power net, different from the first power net; making adetermination whether to connect the first shape to the second shape orthe third shape based on target percentages specified for the first andsecond power nets; if the determination is made to connect the firstshape to the second shape, automatically creating a first via shape in athird layer, different from the first and second layers, that overlapsboth the first and second shapes; and if the determination is made toconnect the first shape to the third shape, automatically creating asecond via shape in the third layer that overlaps both the first andthird shapes.

The making a determination whether to connect the first shape to thesecond shape or the third shape based on target percentages specifiedfor the first and second power nets can include: determining a firstpercentage utilization of the first power net in the free space and asecond percentage utilization of the second power net in the free space;and determining whether the first percentage utilization is less than atarget percentage for the first power net and the second percentageutilization is less than a target percentage for the second power net.

Other objects, features, and advantages of the present invention willbecome apparent upon consideration of the following detailed descriptionand the accompanying drawings, in which like reference designationsrepresent like features throughout the figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a system of the present invention for performing electroniccircuit design, including automatic routing of nets and compaction ofspace of an integrated circuit.

FIG. 2 shows a simplified system block diagram of computer system usedin implementation of the present invention.

FIG. 3 shows a simplified functional block diagram of an exemplary EDAsystem incorporating aspects of the present invention.

FIGS. 4A-4C show a step in a technique of shape creation.

FIGS. 5A-5E show another step in shape creation.

FIGS. 6A-6C show results of a delete hanging technique.

FIGS. 7A and 7B shows results of a prune technique.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows an electronic design automation (EDA) system of the presentinvention for designing an electronic circuit or integrated circuit,including automatic routing of nets and compaction of space of thecircuit. In an embodiment, the invention is software that executes on acomputer workstation system, such as shown in FIG. 1. FIG. 1 shows acomputer system 101 that includes a monitor 103, screen 105, enclosure107, keyboard 109, and mouse 111. Mouse 111 may have one or more buttonssuch as mouse buttons 113. Enclosure 107 (may also be referred to as asystem unit, cabinet, or case) houses familiar computer components, someof which are not shown, such as a processor, memory, mass storagedevices 117, and the like.

Mass storage devices 117 may include mass disk drives, floppy disks,magnetic disks, optical disks, magneto-optical disks, fixed disks, harddisks, CD-ROMs, recordable CDs, DVDs, recordable DVDs (e.g., DVD-R,DVD+R, DVD-RW, DVD+RW, HD-DVD, or Blu-ray Disc), flash and othernonvolatile solid-state storage (e.g., USB flash drive),battery-backed-up volatile memory, tape storage, reader, and othersimilar media, and combinations of these.

A computer-implemented or computer-executable version or computerprogram product of the invention may be embodied using, stored on, orassociated with computer-readable medium. A computer-readable medium mayinclude any medium that participates in providing instructions to one ormore processors for execution. Such a medium may take many formsincluding, but not limited to, nonvolatile, volatile, and transmissionmedia. Nonvolatile media includes, for example, flash memory, or opticalor magnetic disks. Volatile media includes static or dynamic memory,such as cache memory or RAM. Transmission media includes coaxial cables,copper wire, fiber optic lines, and wires arranged in a bus.Transmission media can also take the form of electromagnetic, radiofrequency, acoustic, or light waves, such as those generated duringradio wave and infrared data communications.

For example, a binary, machine-executable version, of the software ofthe present invention may be stored or reside in RAM or cache memory, oron mass storage device 117. The source code of the software of thepresent invention may also be stored or reside on mass storage device117 (e.g., hard disk, magnetic disk, tape, or CD-ROM). As a furtherexample, code of the invention may be transmitted via wires, radiowaves, or through a network such as the Internet.

FIG. 2 shows a system block diagram of computer system 101 used toexecute software of the present invention. As in FIG. 1, computer system101 includes monitor 103, keyboard 109, and mass storage devices 117.Computer system 101 further includes subsystems such as centralprocessor 202, system memory 204, input/output (I/O) controller 206,display adapter 208, serial or universal serial bus (USB) port 212,network interface 218, and speaker 220. The invention may also be usedwith computer systems with additional or fewer subsystems. For example,a computer system could include more than one processor 202 (i.e., amultiprocessor system) or the system may include a cache memory.

The processor may be a dual core or multicore processor, where there aremultiple processor cores on a single integrated circuit. The system mayalso be part of a distributed computing environment. In a distributedcomputing environment, individual computing systems are connected to anetwork and are available to lend computing resources to another systemin the network as needed. The network may be an internal Ethernetnetwork, Internet, or other network.

Arrows such as 222 represent the system bus architecture of computersystem 101. However, these arrows are illustrative of anyinterconnection scheme serving to link the subsystems. For example,speaker 220 could be connected to the other subsystems through a port orhave an internal connection to central processor 202. Computer system101 shown in FIG. 1 is but an example of a computer system suitable foruse with the present invention. Other configurations of subsystemssuitable for use with the present invention will be readily apparent toone of ordinary skill in the art.

Computer software products may be written in any of various suitableprogramming languages, such as C, C++, C#, Pascal, Fortran, Perl, Matlab(from MathWorks, Inc.), SAS, SPSS, Java, JavaScript, and AJAX. Thecomputer software product may be an independent application with datainput and data display modules. Alternatively, the computer softwareproducts may be classes that may be instantiated as distributed objects.The computer software products may also be component software such asJava Beans (from Oracle) or Enterprise Java Beans (EJB from Oracle).

An operating system for the system may be one of the Microsoft Windows®family of operating systems (e.g., Windows 95, 98, Me, Windows NT,Windows 2000, Windows XP, Windows XP x64 Edition, Windows Vista, Windows7, Windows CE, Windows Mobile), Linux, HP-UX, UNIX, Sun OS, Solaris, MacOS X, Alpha OS, AIX, IRIX32, or IRIX64, or combinations of these.Microsoft Windows is a trademark of Microsoft Corporation. Otheroperating systems may be used. A computer in a distributed computingenvironment may use a different operating system from other computers.

Furthermore, the computer may be connected to a network and mayinterface to other computers using this network. For example, eachcomputer in the network may perform part of the task of the many seriesof steps of the invention in parallel. Furthermore, the network may bean intranet, internet, or the Internet, among others. The network may bea wired network (e.g., using copper), telephone network, packet network,an optical network (e.g., using optical fiber), or a wireless network,or any combination of these. For example, data and other information maybe passed between the computer and components (or steps) of a system ofthe invention using a wireless network using a protocol such as Wi-Fi(IEEE standards 802.11, 802.11a, 802.11b, 802.11e, 802.11g, 802.11i, and802.11n, just to name a few examples). For example, signals from acomputer may be transferred, at least in part, wirelessly to componentsor other computers.

FIG. 3 shows a simplified functional block diagram of an exemplary EDAsystem 300 incorporating aspects of the present invention. The EDAsystem includes a number of software tools, any of which may access ashaped-based database model 301 containing an integrated circuit design,or one or more portions of an integrated circuit design. The EDA systemprovides such tools as a graphical user interface 302, global router304, manual editor 306, detail router 308, engineering change option(ECO) engine 310, timing-driven routing engine 312, extraction engine314, data export interface 318, and DSM process engine 320. An EDAsystem may include any number of the system tools shown in FIG. 3, andin any combination. Further, the EDA system may include additional toolsnot shown in FIG. 3.

An EDA system may be a grid-based system or shape-based system. Agrid-based system relies heavily on the concept of a grid and routinggrids. Gridded modeling, however, becomes difficult to implementsuccessfully as the routing and feature sizes become smaller. The amountof data increases according to a square law, which means that tasksbecome increasingly more computationally complex and time-consuming asthe amount of data increase. As feature sizes in integrated circuitscontinue to shrink, more features or geometries may be fitted into thesame unit area of an integrated circuit. Therefore, it is important foran EDA system to handle increasingly complex integrated circuits andprovide output or results quickly.

The techniques of the invention are especially suited for a shaped-basedsystem, which may also be referred to as a gridless system. Ashape-based system has no defined cell size. Each cell, or expansionarea, is as large as possible. In brief, a shape-based system can expandedges, which means that an edge of an enclosing rectangle (or otherpolygon) may be expanded in the direction of the edge as far as desireduntil the edge finds an obstacle. This may be referred to as a “flood”operation.

The shape may be representative of any polygon. For example, the shapemay be a rectangle. The shape may be representative of any polygon ofthe integrated circuit, such as a net, contact, via, transistor gate, ortransistor active area. Blocked edges are edges that cannot be extendedbecause they are blocked by a perimeter of another rectangle, such asanother segment, net, or obstacle. Once an obstacle is encountered, thena shape-based approach floods around the obstacle—making a ninety degreeor other angle (any angle may be used such as 30 degrees, 35 degrees, 36degrees, 42 degrees, 45 degrees, or 60 degrees) turns as needed to routearound the obstacle.

Chip design, be it analog, custom or digital, will increasingly sufferfrom timing and signal integrity issues, and in particular crosstalk, asgeometries continue to decrease and ever more fine wires are introduced.Gridded solutions are not flexible enough to resolve these issues, letalone achieve a high rate of routing completion. A high performancetiming and crosstalk-driven routing solution will become a mandatoryrequirement in physical design.

The grid-based approach offers fast routing but requires customizationto handle off-grid connections and is inefficient for post-route timingand signal integrity optimizations. When net widths and spacings must bechanged to reduce resistance or cross-talk, grid-based approaches wastespace by moving nets to the next available grid and waste time byresorting to rip-up and re-route techniques. Gridded systems are notgood at irregular intervals, irregular spacings, or routing things thatdo not fit onto a regular grid.

The gridless approach easily handles off-grid connections and isefficient for post-route optimizations. In a shape-based or gridlesssystem, the layout may be a gridless layout, which means there is nogrid which structures or polygon of the layout are associated with,other than a grid for the relevant manufacturing process, if any.

In an embodiment, the structure of database 301 facilitates shape-basedoperations. For example, a structure of this database may include anobstacle tree having nodes and leaves containing the obstacles of anintegrated circuit. This tree structure permits rapid determination ofwhere obstacles are when doing operations on the database, such asrouting nets.

In FIG. 3, the EDA system 300 includes one or more of the componentsdiscussed below, in any combination. One skilled in the art willrecognize that one or more of components shown in FIG. 3 may not berequired to practice specific aspects of present invention. For example,when DSM process engine 320 is omitted from system, the system couldstill perform automatic routing of interconnect, but without providingDRC checking capabilities.

A graphical user interface 302 provides users a graphical interface inwhich to perform operations on the integrated circuit design. Forexample, the user can view the integrated circuit using the graphicalinterface. The user may use the mouse and cursor to select a particularpolygon or feature, such as a net. The user may expand or zoom intoareas of the integrated circuit design.

A global router 304 is an automatic routing engine that coarsely routesinterconnects of the integrated circuit, thus enabling large designs tobe routed more rapidly and completely. The global router may alsoprovide visual and quantitative analysis of the congestion in the designby highlighting problem areas that can be fixed by incrementaladjustments to the floor plan. The global router is sometimes referredto as a coarse router because it provides generally the routes for theinterconnect, and may work in conjunction with a detail router 308(discussed below) to place the geometries of the interconnect.

A manual editor 306 is a shape-editing suite for creating or editingmetal, keep-outs, routing areas, and the ability to partition a designinto smaller areas. These areas can then be worked upon individually andcan be recombined at a later stage to complete the design. Full on-linedesign rule checking (DRC) ensures that manual operations are completederror-free first time. Powerful tools automatically push-aside existingwiring to make way for new wires and semiautomatic routing tools quicklyclose down troublesome nets by allowing the user to guide the routingengine around complex areas of the design.

The detail router 308 is an automatic router that completes the wiringin a design by determining the specific routes for each interconnect.The detail router may complete a portion of the wiring for design, suchas for sections or specified cells of the design, or may complete allthe wiring of the design. The detail router may route starting fromscratch or from partially completed routing. In an implementation, theglobal router determines the general route paths for the interconnect,and the detail router takes this routing information from the globalrouter and puts in the physical detailed geometries of the tracks andvias.

An engineering change order (ECO) engine 310 provides a capability tohandle late stage ECO changes. Every element of the design can bemodeled incrementally, thus eliminating the need to ever restart thephysical design, no matter what changes may need to be made fromupstream or downstream processes in the design. ECO engine capabilitiescan include the ability to shove or push cells aside to make space fornew or relocated instances, and the ability to drop groups of componentsand automatically find legal placement sites for them minimizing thedisruption to the design. When pushing or pulling cells, the wiresremain connected to the cells and the wires lengthen, shorten, and moveas needed, if possible, to keep the connections. The detail router canthen repair any violating interconnects and stitch-up any newlyintroduced interconnects, with minimum impact, ensuring circuitstability is never compromised.

A timing-driven routing engine 312 provides RC timing analysis ofinterconnects. Used in concert with the detail router, the timing enginecan determine the path of least delay for critical nets. Furthermore,the timing engine, in concert with an extraction engine, can activelyselect a longer path with a lower associated delay (e.g., due to lowercapacitance) in preference to a shorter but slower route.

An extraction engine 314 is provided. Utilizing a unified, high-speed RCextraction engine, the crosstalk functionality accurately calculates thecoupling between victim and aggressor signals. This same technology isthen used to identify potential problems, and automatically implements aDRC correct solution without changing the path of the signalunnecessarily. In addition, signal-to-signal (or within and betweenclasses of signals) spacing rules can be applied, and fully controllableautomatic shielding can be used to protect particularly sensitivesignals. The user is provided with unprecedented control over theresistance and capacitance in the signal path. Again, using the advancedbuilt-in RC extraction technology, the user can separately control pathresistance and capacitance, which is particularly useful for analog andmixed signal design.

In an implementation, the global router and detail router are linked tothe extraction engine. So, for example, when running, the global routeror detail router, or both, can call the extraction engine to obtain RCextraction information. The global router, detail router, or both, mayuse the RC extraction information when creating the interconnect routes.For example, the detail router may obtain RC extraction info from the RCengine in order determine whether an interconnect route meets currentdensity rules, and widen the interconnect width as needed. More detailsare discuss in U.S. patent application Ser. Nos. 10/709,843 and10/709,844, both filed Jun. 1, 2004 and incorporated by reference.

In a specific embodiment, an RC extraction driven constraints managerhas been enhanced to ensure matching on a per-layer basis as well as thewhole net or subnet. There is an increasing requirement in today'sdesigns to match length, time, resistance and capacitance across nets ona per-layer basis. This ensures total net constraints are met as beforebut also guarantees designated nets can match on a per-layer basis.

The tightly coupled, high-speed RC extraction engine is used both duringrouting (global router or detail router, or both) and for post-routingextraction to reach timing closure in record time. Integrated timinganalysis and curative features enable the management of delay within thedesign; the matching of delays within and between multiple nets; thesharing of delay between many nets in a signal path; and reducing thedelay in critical nets by minimizing resistance and capacitance.Intelligent lengthening increases the delay of the faster nets,preventing shoot-through.

The detail router can address current density issues in analog design,to help achieve an optimum routing result for the entire design, andsave valuable design time. The current information which is used todrive this current density functionality may come from, for example, afront-end schematic engine or simulation engine. The router canautomatically route a net at varying widths to guarantee sufficienttrack widths at every point in the topology of the net to carry allcurrent requirements. DRC and process checking tools locate anyinsufficient width areas that may exist in any routing, includingautomatically generated routing, manual routing, and importedprerouting.

A data export interface 316 is provided so data of the EDA system 300may be exported for other processes. For example, output from the EDAsystem may be passed through the export interface to other EDA systemsor software tools provided by other manufacturers. The export interfacewould provide output in a form, format, or structure, acceptable byprocess or software tool to which it is being exported.

A data import interface 318 provides the means to import data, such as acircuit layout, netlist, or design constraints. The data to be importmay be in various formats including data saved from other EDA systems orsoftware tools. In addition, the source of the data may be a database,floppy drive, tape, hard disk drive, CD-ROM, CD-R, CD-RW, DVD, or adevice over a communication network. Some examples of import formatsinclude text, ASCII, GDSII, Verilog, SIF, and LEF/DEF.

A DSM process engine 320 is provided. The DSM process engine does designrule checking (DRC). Design rule checking locates and highlights where adesign is breaking process design rules. For example, a design rule isthe minimum spacing between metal lines (i.e., geometries on a specificlayer). A design rule may be the minimum width of a metal line. A designrule may be a minimum polysilicon-to-diffusion spacing. There are manyother design rules for a typical process. Some design rules are forchecking geometries within a single layer, and some design rules are forchecking geometries of two or more layers.

A user may design an integrated circuit using a system such as shown inFIG. 3. A representative flow for designing an integrated circuit isoutlined in steps 1 to 8 below. Step 5 is further subdivided into threesubsteps.

Integrated Circuit Design Flow

1. Provide Circuit Specification

2. Create Circuit Design

3. Generate Netlist

4. Simulate Performance and Verify Functionality of Circuit Design

5. Generate Layout

5a. Layout Devices

5b. Connect Devices

5c. Connect Blocks of Circuitry

6. Physical Verification and Design Checking

7. Create Masks

8. Fabricate Integrated Circuit

Although the steps above are listed in a specific order, the steps maytake place in any order, as desired and depending on the specificapplication. These are general steps that may be applied to designing anintegrated circuit including custom, a gate array, standard cell, fieldprogrammable logic, microprocessor, digital signal processor,microcontroller, system-on-a-chip (SOC), memory, ASIC, mixed signal,analog, radio frequency (RF) or wireless, and others. There may beadditional or other steps, which may replace one or more above steps.Certain steps may be repeated. For example, after generating a layoutfor a circuit design, the step of simulating performance and verifyingfunctionality may be performed again. This time, the parasitics and RCconsiderations from the layout can be back-annotated into the netlist orcircuit design, and the design simulated again. The results of thissimulation will presumably be more accurate because more preciseinformation is provided.

In step 1 of the flow, a circuit specification is provided. This is aspecification or description of what the integrated circuit or circuitwill do, and what the performance will be. For example, the integratedcircuit may be a memory integrated circuit with particular address inputpins and input-output (I/O) pins. Integrated circuit performance may bequantified terms in AC and DC performance. For example, AC performancerefers to propagation delays, maximum clock frequency, clock-to-outputdelay, hold time, and other similar parameters. DC performance refers tomaximum supply current, maximum and minimum supply voltage, outputcurrent drive, and other similar parameters.

In step 2, an engineer creates a circuit design that presumably willmeet the circuit specification. This circuit design may includetransistors, resistors, capacitors, and other electronic components. Theengineer uses these electronic components as building blocks of thedesign, interconnecting them to achieve the desired functionality andperformance. The engineer may make a custom design using electroniccomponent building blocks or use a gate array, where the building blocksare sets of cells set by the gate array manufacturer. The design may beinput using a graphical design tool such as schematic capture program,and any other design tool may be used. The circuit may be describedusing a high-level design language (HDL). These design tools will createa netlist (step 3) of the circuitry, which is a listing of thecomponents of the devices and their interconnections.

During the design phase, the engineer simulates the performance andverifies the functionality of the circuitry (step 4). There aretransistor and process models to model the components. Some simulationtools include Spice, which performs circuit simulation, and Verilog,which performs functional and timing verification. This is where theelectrical information for current density routing is generated.

After deciding upon an initial circuit design, the engineer beginslayout (step 5) of the circuitry. Layout refers to making thethree-dimensional dispositions of the element and interconnections tomake an integrated circuit. Making an integrated circuit is a layer bylayer process. Some layers of an integrated circuit are diffusion,polysilicon, metal-1, metal-2, contact, via, and others. There may bemultiple layers of the same material, but on different layers. Forexample, diffusion and polysilicon layers are used to make MOStransistors (step 5a). For example, metal-1 and metal-2 are twodifferent layers, where metal-1 is below the metal-2 layers. These metallayers may be connected together using a via. Metal is typically usedfor interconnections (step 5b) and supplying power and ground to thedevices.

Software tools may be used to help with the layout of the circuit, suchas the automatic routing of interconnect (steps 5b and 5c). Theinterconnect may be between devices. Devices and circuitry may begrouped into blocks or cells having inputs and outputs. The interconnectmay be between these blocks or cells (step 5b).

In step 6, after or while the layout is generated, the physical designis verified and checked. For example, some of these operations mayinclude layout-versus-schematic (LVS) checking, electrical rule checking(ERC), design rule checking (DRC), layout simulation (especially foranalog circuitry), power analysis, and timing analysis. Physicalverification and design checking is often iterative. Based on the designcheck, a design engineer or user may make changes to the design orlayout, or both and the design may be rechecked in order to make sureany areas of concern or design errors have been cleared.

The result of layout is data (e.g., provided in GDSII or other format)that is used to make the masks (step 7). The masks are used to fabricatethe integrated circuit (step 8) using a photolithography process.Typically, there are many “copies” of the same integrated circuitedfabricated on the same wafer. Each integrated circuit is a “die” on thewafer. Good dies are separated from the bad dies. The good dies aresawed and packaged. Packaging generally includes encapsulating the diein plastic or other material, and connecting pads of the integratedcircuit to pins of the package, where the integrated circuit can beinterfaced.

The invention provides a technique for filling vacant areas ofintegrated circuit design. Vacant areas of a layer are those areas ofthe area where no drawn polygon is resides. These vacant areas arefilled with metal or another conductor connected to a supply line suchas power or ground. Compared to layout engineers manually drawing shapesin an unused area, while trying to conform to DRC rules (which is verytedious and time consuming), the technique of the invention is acomputer-implemented or automated technique.

For some particular integrated circuit designs, it is desirable (orrequired) to fill vacant areas of a routed design with metal or otherconductive material. This approach is typically performed on metalslayers of the integrated circuit design, but can be applied to otherlayers as desired. This application describes the approach with respectto metal layers, but one of ordinary skill in the art would recognizethe technique is applicable to other types of layers.

In an implementation, this metal is connected to a supply line or net,such as power and ground. In other implementations, the metal can beleft floating or connected to a line such as a signal line or a high ornegative voltage line (e.g., output of a charge pump).

This application provides a specific example of technique of theinvention. Some sample rules include: Each layer may have any number ofvoltages that the filled nets can be connected to. For example, thevoltage nets on a particular layer may be VCC and ground or GND. Theremay be multiple VCCs, such as VCC1, VCC2, VCC3, and so forth. There maybe multiple grounds, such as GND1, GND2, GND3, and so forth. There maybe other voltage nets such as VPP, VBB, or others.

Each layer to be filled will have a list of nets to be used withapproximate relative percentages. The user can specify each of thetarget percentages. For example, a metal-2 layer has a power fillingcriteria of: 40 percent for VCC1, 40 percent for VCC2, and 20 percentfor GND. The total of the percentages should equal 100 percent. If thetotal is less than or greater than 100, the computer may display amessage give the user a warning. The values for each power net can haveany value such as 5, 10, 15, 25, 28, 30, 35, 40, 45, 50, 60, and others.

Additionally, there can be system defaults for each of the power netvoltage layers. For example, the system default may be to allocate thefree space evenly among the power nets. If there are five power nets,then each net will be allocated 20 percent (i.e., 100 divided by thenumber of power nets—5). Typically there will be at least two powernets, VCC and GND.

In a specific implementation, the percentage specified for each powernet is the percentage for the added nets to fill the free space. If rulefor layer L specifies ratios for nets (e.g., N1, N2, and N3), the actualpercentage for N1 is the area of N1 on that layer as a percentage of thetotal area of (N1+N2+N3) on that layer. This includes pin, metal, andfillers, but excludes routing (e.g., track and vias).

In another implementation, the percentage specified may be with respectto the total power net geometries on the layer, not just the nets thathave been added in the free space. For example, if 40 percent isspecified for VCC1, then the technique will attempt to target the totalVCC1 geometries to be 40 percent of all power nets of the layer. In thisimplementation, the target percentages specified for the nets added inthe free space may not need to equal 100.

Shapes created to fill vacant areas should have widths within specifiedminimum and maximum constraints. In order to satisfy a max_widthconstraint, a large vacant area will be filled with stripes of metalwhere the stripes are consistent with the general direction of metal onthat layer.

There can be contraints based on orientation (e.g., north, south, east,west, vertical, or horizontal), such as a max_width which is differentfrom a max_height. Then, vertical stripes can have a maximum width thatis independent of and different from the horizontal stripes. Forexample, the horizontal width maximum is 2 microns, while the verticalwidth maximum is 1.8 microns. Different width constraints widths fordifferent orientations may be used to compensate for optical effectssuch as lens astigmatism during fabrication of an integrated circuit.

In an implementation, the power fill technique has three subroutines(each of which can be implemented as a tool):

1. Shape Creation

2. Delete Hanging

3. Prune

Shape Creation Method

The shape creation method creates shapes of geometries in the free spaceof the layer. These shapes are assigned a property to indicate that theywere automatically generated in the free space. That way a user will beable to distinguish and view which shapes were automatically generated.

The following describes how an individual layer is populated with metalshapes on the appropriate nets. This method is documented assuming thatthe layer is y-biased. For an x-biased layer, “bottom” would read“left,” and “top” would read “right” and so forth.

Two subtly different types of metal filler are considered: Firstly,metal that abuts existing pin/metal on that layer. Secondly, metal thatis completely in free-space on that layer.

The free-space technique includes the following steps:

1. Start with a list of rectangles comprising a single rectanglecovering the complete area for which filling is required. This list isused to represent the vacant space on that layer. One approach startsfrom a lowermost layer and propagates upward. So, if there are threedifferent layers of metal. The metal-1 layer would be the first to beprocessed. Then metal-2 and metal-3 would sequentially follow. In otherapproaches, the uppermost layer may be processed first.

2. For each existing shape on this layer:

2a. Grow it by the maximum spacing between it and power metal

2b. Subtract the grown shape from the rectangle list

2c. Discard any rectangles that are smaller than a min width in either xor y.

FIGS. 4A-4C show the effect of subtracting a grown rectangle 402 basedon a metal object 405 from a rectangle. In FIG. 4A, first a selectionrectangle 406 is drawn to cover and select the complete area wherefilling is desired. The selection rectangle is on or overlaps (at leastpartially overlaps) an existing shape or geometry 405. The techniqueoversizes shape 405 to obtain rectangle 402. The amount of the oversizedepends on the design rules for metal-to-metal spacing specified forthat layer. For example, if the metal-to-metal spacing specify 0.5microns, then rectangle 405 will be oversized by 0.5 microns on eachsize to obtain rectangle 402.

Grown rectangle 402 is subtracted from rectangle 406. As shown in FIG.4C, the resulting effect is that this rectangle gets replaced by twosmaller overlapping rectangles, rectN 408 on a north side and rectE 411on an east side. South and west residual rectangle are discarded on thebasis of being too small. As shown in FIG. 4B, the west residualrectangle 414 is shown in broken lines and is discarded because itswidth is less than a minimum metal width permitted. For example, theminimum metal width permitted by the design rules may be 0.3 microns.

A result of step 2 (steps 2a to 2 c) is a list of rectanglesrepresenting the fillable space on that layer. This is the free space onthe layer that can be filled with additional shapes.

3. Assuming that we are working on a y-biased layer, in implementation,find the extreme west free-space rectangle (or extreme south for anx-biased layer). For example, in FIG. 5A, rectangle 509 qualifies as theextreme west free-space rectangle. This is because the left edge ofrectangle (indicated by reference number 509) is further left than anyof the other rectangles in FIG. 5A. Reference number 509 refers to alower, leftmost point of rectangle 503.

The technique may use any rectangle as a starting point for the process.For example, the technique may start with the uppermost, rightmost, orbottommost rectangles.

A limit 515 will be calculated as:Limit=extreme west coordinate+max_width.

The limit line 515 is a vertical line positioned at a max_width distancefrom point 509. So, if max_width is 2 microns, limit 515 will be 2microns from point 509.

4. Grow an island starting from this rectangle, by recursively lookingfor other free-space rectangle which when truncated to “limit,” overlapsthe island rectangle by min width in both dimensions (vertically andhorizontally). FIG. 5B shows an example of a grown island 518 for FIG.5A.

5. Take the outline of the rectangles that constitute the island, andtrim it according to the minimum step rule: any steps on this outlinethat are too small, result in the shape being shrunk. The portions ofthe rectangles greater than permitted by the limit line are removed. Aresulting shape 521 from FIG. 5B is shown in FIG. 5C.

6. Determine which of the relevant power nets are overlapped by thisshape. This is done by looking for pin or metal on other layers. In FIG.5D, there is a shape 526 for a power net on a different layer than shape521 that overlaps shape 521. It will be possible to connect power fromshape 526 to shape 521 using a via connection.

As discussed above, an approach starts from the lowermost layer andpropagates upward. In an implementation, the technique considers powernets added to the vacant areas by this technique during a previousiteration for a lower layer. Specifically, for example, shape 526 mayhave been added to the free space in a previous layer by a technique ofthis invention.

7. Order these candidate nets by decreasing deficit (i.e., required fillquota minus actual fill quote). The net associated with the last pieceof fill metal created is relegated behind any deficient nets, in orderto try to avoid adjacent fillers being associated with the same net.

FIG. 5E shows an example of this step. There are multiple shapes 526 and528 for power nets on a different layers than shape 521 that overlapsshape 521. Shape 526 is connected to VCC1, while shape 528 is connectedto VCC2. If at that point, VCC1 is at 38 percent (where 40 percent isthe target) and VCC2 is at 32 percent (where 40 percent is also thetarget), the technique will preferentially connect shape 521 to 528instead of 526 because VCC2 is lower (by percentage or absolute value)than the target more than VCC1 is.

N1, N2, and N3 are the three different power nets which are used to fillthe vacant areas according to the specified percentages. In a technique,if N1 is very low, and N2 is slightly low, and N3 is high, and theproposed filler overlaps all three nets, then N1 will be given highestpriority because it is most deficient. However if the previous fillerassigned was an N1, then N2 is favored, as it is also deficient. Thisapproach is used to try to reduce the occurrence of adjacent fillers onthe same net.

As one of ordinary skill in the art will appreciate, the percentagerules are approximate, because by the time hanging filler are removedand prune, the actual percentages could change. Therefore, specifiedpercentages are used as guidelines.

8. Create metal using the outline determined above and the firstcandidate net. If this metal is legal, try to strap it to theoverlapping metal on this net by inserting vias. For FIG. 5D, a via(layer not shown in the figure) is added between shapes 521 and 526. InFIG. 5E, the technique adds via (layer not shown in the figure) toconnect shapes 528 and 521.

If strapped successfully, then the metal filler is accepted and the listof remaining holes is updated by applying step 2 to this shape.

If the metal was illegal, or strapping failed, then try next candidatenet, and so forth. If shape 521 cannot be connected to a power net onanother layer or to another power net on the same layer (see abuttingalgorithm below), shape 521 will be discarded (e.g., removed) if for thetechnique it is not desirable to have floating metal.

9. While there are holes remaining, repeat from step 3.

An abutting algorithm includes the following steps (which are similar tothose described above). This abutting technique attempts to strap orconnect a shape added to the free space to another power net on the samelayer. This other power net may be one that the user drew into the layeror one that may be entered previously by the technique of the invention.This abutting technique may be performed before (or after) attempting tostrap or connect a shape to a power net on a different layer.

These steps are applied to each pin or metal item on relevant powernets, within the area being filled, and on the layer being processed.

1. Start with a list of rectangles comprising a single rectangleextended from the bottom edge of item to bottom edge of area beingfilled.

2. Subtract oversized used space from this rectangle list. See FIG. 4.

The oversizing is applied using the required spacing between the objectand power metal. Any residual free-space rectangles that are smallerthan min width in either dimension are discarded.

The result of this step is a list of rectangles representing thefillable space beyond the pin/metal.

3. Calculate Limit=west coordinate of edge+max_width

4. Grow island as in step 4 of the free-space technique above

5. Trim it as in step 5 of the free-space technique above

6. Create metal shape using trimmed outline as per step 8 of thefree-space technique above, except that in this case the net is known.

Repeat steps 2-6 using the top edge of the pin or metal item.

Delete Hanging Method

In a specific implementation, there is a condition to be able toidentify and delete redundant power fillers. Essentially a power filleris redundant unless it connects directly or indirectly to at least twoislands containing a real pin or metal. A technique of the inventiondetermines whether a metal filler is redundant or hanging. If redundantor hanging, the metal filler is removed.

In FIGS. 6A-6C and 7, nets running in the horizontal direction aremetal-1, while nets running in the vertical direction are metal-2. Metalwith solid fill is a real pin or metal, while metal in shaded fill is ametal filler. Vias for strapping the intersections of metal-1 andmetal-2 are not shown.

Specifically, geometries or shapes 603, 604, 605, and 607 are metal-1and real pin or real metal. These geometries were drawn or added to thelayer by the user and not automatically generated by a technique of theinvention. Lines 613, 615, and 617 are also metal-1, but are metalfiller. Lines 623, 625, and 627 are metal-2 and metal filler. Line 629is metal-2 and a real pin or real metal. Metal filler are shaped addedby a power fill technique (to fill vacant areas or free space) of theinvention.

FIG. 6A shows a layout where all fillers (numbered 613 and 623) areredundant. There are vias between shapes 623 and shape 603, and shapes623 and shape 613. However, there is no flow path through the filler,which makes the filler redundant.

FIG. 6B shows a layout with no redundant fillers (numbered 613 and 623).Compared to the situation in FIG. 6A, there is a shape 629 which isconnected through a via to shape 613. Current on shape 604 will be ableto flow through the filler to shape 629. Therefore, none of the fillerare redundant in this case.

FIG. 6C shows a layout where four fillers (numbered 615 and 623) on theleft are redundant, while the other fillers (three fillers on the right,numbered 617, 625, and 627) are not. Current from shape 605 will be ableto flow through fillers 625, 627, and 617 to shape 609 and 607; thesefillers are not redundant. However, fillers 623 in FIG. 6C are redundantas explained for FIG. 6A.

A technique to determine whether or not a particular filler is redundantis as follows:

1. If the filler has less than two physical contacts, it is hanging.

2. Define an island to be a group of physically connected items on alayer. Hence, for example, FIG. 6C has four islands on metal-1 and fiveislands on metal-2.

3. Define a rocky island to be an island that contains at least one pinor real metal.

4. Traverse the tree structure as shown in the above diagrams, startingfrom the filler. Do not walk beyond pin or real metal items. If morethan one rocky island is encountered from different points on theoriginal filler, the filler is not redundant. If, for example a fillerhas a via contact which in turn contacts two pins on different layers,then that is only regarded as a single rocky island contact as bothisland are reached through the same contact point of the filler.

Prune Method

Having created metal fillers and removed redundant fillers, we are leftwith useful fillers which may well extend beyond their via contacts orcontain bulges that serve no purpose.

FIGS. 7A and 7B shows an example of the prune technique. Geometries orlines 712 and 715 are metal-2, while the other geometries 717 aremetal-1 fillers.

The method for achieving this pruning effect is as follows:

for each line of the outline shape  if it faces the layer bias (i.e.,horizontal in this case)   it is a bracket (i.e., the previous and nextlines are in   the same vertical direction)    prune this bracket(limiting the prune to extreme contact if any)    restart from thebeginning of the shape outline

This technique results in the pruning of the three brackets as shown inthe changes from FIG. 7A to 7B. For example, region 722 in FIG. 7A has avery narrow width and is removed, so it is not in the shape of FIG. 7B.Also, the regions of the filler above shape 712 (indicated by referencenumber 725) and below shape 715 (indicated by reference number 728) arealso removed. There are vias or contacts connecting the metal filler toshapes 712 and 715. Regions 725 and 728 extend beyond a desired distancefrom the via.

This description of the invention has been presented for the purposes ofillustration and description. It is not intended to be exhaustive or tolimit the invention to the precise form described, and manymodifications and variations are possible in light of the teachingabove. The embodiments were chosen and described in order to bestexplain the principles of the invention and its practical applications.This description will enable others skilled in the art to best utilizeand practice the invention in various embodiments and with variousmodifications as are suited to a particular use. The scope of theinvention is defined by the following claims.

What is claimed is:
 1. A method comprising: using a computer,automatically creating a first shape comprising rectangles that isrepresentative of free space on a first layer of an integrated circuitdesign; automatically creating a second shape comprising rectangles thatis representative of free space on a second layer of the integratedcircuit design, wherein the second layer is different from the firstlayer; automatically creating a first via shape in a third layer,different from the first and second layers, that overlaps both the firstand second shapes; determining whether the first shape is furthercoupled to a third shape on a fourth layer, different from the first andsecond layers, wherein the third shape is representative of a powervoltage net; and if the first shape has a further coupling to the thirdshape, not discarding the first shape and the first via shape.
 2. Themethod of claim 1 comprising: if the first shape does not have a furthercoupling to a third shape, discarding the first shape and the first viashape.
 3. The method of claim 1 wherein a distance from a leftmost edgeof the first shape to a rightmost edge of the first shape does notexceed a maximum width specified for the automatic creation.
 4. Themethod of claim 1 comprising: upon request by a user, showing only theautomatically generated shapes of the first layer on a display of thecomputer.
 5. The method of claim 1 comprising: determining whether thefirst shape is further coupled to a fourth shape on a fourth layer,different from the first and second layers, wherein the fourth shape isrepresentative of a ground voltage net; and if the first shape has afurther coupling to a fourth shape, not discarding the first shape andthe first via shape.
 6. The method of claim 5 comprising: if the firstshape does not have a further coupling to a fourth shape, discarding thefirst shape and the first via shape.
 7. The method of claim 1comprising: if the first shape does not have a further coupling to athird shape, discarding the first shape and the first via shape;determining whether the first shape is further coupled to a fourth shapeon a fourth layer, different from the first and second layers, whereinthe fourth shape is representative of a ground voltage net; if the firstshape has a further coupling to a fourth shape, not discarding the firstshape and the first via shape; and if the first shape does not have afurther coupling to a fourth shape, discarding the first shape and thefirst via shape.
 8. The method of claim 1 wherein the automaticallycreating a first shape comprising rectangles that is representative offree space on a first layer of an integrated circuit design comprises:determining where the first rectangle overlaps a previously drawn secondrectangle on the first layer; using at least one computer processor,oversizing the second rectangle to obtain a third rectangle; using atleast one computer processor, subtracting the third rectangle from thefirst rectangle to form a fourth rectangle, fifth rectangle, and sixthrectangle, wherein the fourth, fifth, and sixth rectangles each have asmaller area than the first rectangle and the fourth, fifth, and sixthrectangles overlap; if the sixth rectangle has a smaller width than afirst minimum width, discarding the sixth rectangle while keeping thefourth and fifth rectangles; starting with an edge of the fourthrectangle, growing an island that extends from the edge to a limit lineat a second minimum width; and discarding portions of the fourth andfifth rectangles beyond the limit line to obtain a first shapecomprising rectangles.
 9. The method of claim 1 comprising: determiningwhether the first shape is further coupled to a fourth shape on a fourthlayer, different from the first and second layers, wherein the fourthshape is representative of a GND voltage net; if the first shape has afurther coupling to a fourth shape, not discarding the first shape andthe first via shape; providing a first target percentage and a secondtarget percentage, wherein a sum of the first and second targetpercentages is less than or equal to 100, the first target percentage isrepresentative of a percentage of rectangles in the first layer coupledto the power voltage net, and the second target percentage isrepresentative of a percentage of rectangles in the first layer coupledto the ground voltage net; and automatically coupling rectangles to thepower or ground voltage nets according to the first target percentageand the second target percentage.
 10. The method of claim 1 wherein whenthe first shape is coupled to the third shape, the first shape and thefirst via shape is not discarded, this results in the first shape beingcoupled to the second shape through the first via shape in the thirdlayer, and the first shape being coupled to the power voltage netthrough the second and third shapes, thereby coupling free space on thefirst layer to the power voltage net.
 11. The method of claim 1comprising: by way of not discarding the first shape and the first viashape, transforming free space on the first layer into the power voltagenet.
 12. The method of claim 1 comprising: after the not discarding thefirst shape and the first via shape, denoting the first layer as beingrepresentative of the power voltage net.
 13. The method of claim 1wherein the creating a first shape comprising rectangles, transformsfree space on the first layer into the first shape, wherein the secondshape comprising rectangles, transforms free space on the second layerinto the second shape, wherein the creating a first via shape in a thirdlayer, different from the first and second layers, that overlaps boththe first and second shapes, transforming the first layer and the secondlayer from being two different floating layers so the first layer andsecond layer are coupled together, and wherein the determining whetherthe first shape is further coupled to a third shape on a fourth layer,different from the first and second layers, wherein the third shape isrepresentative of a power voltage net, transforming the second layerfrom being a floating layer to being coupled to the power voltage net.14. The method of claim 1 wherein the first layer and third layer willbe used to create a mask set for a fabrication of an integrated circuit.15. The method of claim 1 wherein the automatically creating a firstshape comprising rectangles that is representative of free space on afirst layer of an integrated circuit design comprises: determining wherethe first rectangle overlaps a previously drawn second rectangle on thefirst layer; using at least one computer processor, oversizing thesecond rectangle to obtain a third rectangle; using at least onecomputer processor, subtracting the third rectangle from the firstrectangle to form a fourth rectangle, fifth rectangle, and sixthrectangle, wherein the fourth, fifth, and sixth rectangles each have asmaller area than the first rectangle and the fourth, fifth, and sixthrectangles overlap; if the sixth rectangle has a smaller width than afirst minimum width, discarding the sixth rectangle while keeping thefourth and fifth rectangles; starting with an edge of the fourthrectangle, growing an island that extends from the edge to a limit lineat a second minimum width; discarding portions of the fourth and fifthrectangles beyond the limit line to obtain a first shape comprisingrectangles; determining whether the first shape is further coupled to afourth shape on a fourth layer, different from the first and secondlayers, wherein the fourth shape is representative of a ground voltagenet; if the first shape has a further coupling to a fourth shape, notdiscarding the first shape and the first via shape; providing a firsttarget percentage and a second target percentage, wherein a sum of thefirst and second target percentages is less than or equal to 100, thefirst target percentage is representative of a percentage of rectanglesin the first layer coupled to the power voltage net, and the secondtarget percentage is representative of a percentage of rectangles in thefirst layer coupled to the ground voltage net; and automaticallycoupling rectangles to the power or ground voltage nets according to thefirst target percentage and the second target percentage.
 16. The methodof claim 15 wherein a distance from a leftmost edge of the first shapeto a rightmost edge of the first shape does not exceed a maximum widthspecified for the automatic creation.